IBM PC-Compatible High Speed Signal Acquisition Design Using the 51C259H CHMOS Dynamic RAM
by Steve M. Gehlbach
Intel Application Note AP-250, published in April, 1985.
This application note illustrates the use of the fast Static Column Mode of Intel's new CHMOS Dynamic RAMs in the design of a digital signal acquisition device. The device can acquire up to 128K Bytes of digitized signal at continuous rates of greater than 14 MHz by alternating between two 64K Byte sections of RAM. No buffering of the data is required, and the design is easily extendable to 256K Bytes of storage. IBM PC Bus compatibility is also included.